1. Field of the Invention
The invention relates to a process for forming shallow drain extension regions in semiconductor devices.
2. Description of the Related Art
There is a continuing quest to define and produce transistors having ever-smaller overall cell geometries and that are capable of operating at increasing switching speeds. For the purposes of this application, cell geometry is defined as the two-dimensional surface area required for implementing a single, integral active logic element, typically an N- or P- channel transistor resistor or a pair of complementary transistors. Cell geometry can be distinguished from transistor geometry in that the latter refers to the three-dimensional structure of a single integral logic element.
A great deal of time and effort has been spent on producing the so-called LIGHTLY DOPED DRAIN-SOURCE (LDD) semiconductor device, wherein shallow extension regions are provided near the edges of the gate structure at the point within the transistor where a large degree of electric field strength occurs. Typically, these extension regions are provided adjacent to the source or drain (referred to collectively herein as the "active" regions) in a typical semiconductor device. (For purposes of this disclosure, the term "active region" is defined as any surface conductive region in a typical semiconductor device where a connection is made to elements external to the device such as, for example, a source or drain in an MOS device.) The typical LDD structure involves providing narrow, self-aligned lightly-doped regions between the device channel and more heavily doped source-drain diffusions in the device. It has been repeatedly shown that significant improvement in breakdown voltages, hot electron effects, and short channel threshold effects can be achieved using LDD regions, thereby allowing transistor operation at higher voltages and shorter channel lengths. Indeed, LDD technology is extremely advantageous in sub-micron channel length devices.
Typically, the lightly-doped drain region is extremely shallow so as to minimally impact all other electrical characteristics of the drain-to-channel interface and to maximize the corresponding reduction of the electric field strength within the lightly-doped drain region. This reduction in field strength directly reduces the transfer of energy to charge carriers at the oxide/substrate interface with the corresponding reduction in the number of charge carriers injected into the gate oxide.
Typical devices constructed with LDD regions are shown in Ogura, et al. titled "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor", IEEE publication, copyright 1980, and U.S. Pat. Nos. 5,257,095, 4,590,663, 4,282,648, and 4,366,613.
In general, the LDD structure can be fabricated using conventional planar silicon-gate processing techniques and optical lithography. One such conventional process for forming LDD regions is shown in FIGS. 1-3. In FIG. 1, the P type silicon substrate 20 is first covered with a thermally grown silicon dioxide layer 22. Polysilicon layer 24 is next deposited onto the oxide layer 22, and the oxide layer and polysilicon layer 24 etched using any conventional photolithographic etching techniques to form a gate structure 26. A light implantation of n- type dopants 28 may thereafter be provided to form a shallow, lightly doped region 30. As shown in FIG. 1, the gate structure 26 will block implantation of the n-ions below the gate region and the remaining portion of oxide layer 22.
As shown in FIG. 2, spacer regions 32 are formed by depositing a photoresist material or oxide over the surface of the gate structure 26 and the shallow n-region 30, followed by chemical etching. As shown in FIG. 3, a subsequent deep n+ implant is utilized to form the deep active regions 34 in P substrate 20.
While the prior art method for implementing the LDD regions in semiconductor devices has proved useful, improved methods are constantly being sought for reducing the production time of devices, increasing the accuracy of the implant dosage, and reducing the number of process steps required to manufacture such devices.